Conventionally, after grinding, cleaning and etching steps, the surface(s) of the semiconductor wafers is (are) smoothed by removal polishing.
In the case of single-side polishing (SSP), semiconductor wafers are held during processing on the rear side on a support plate using cement, by means of vacuum or by means of adhesion.
In the case of double-side polishing (DSP), semiconductor wafers are introduced loosely into a thin carrier and are polished on the front and rear sides simultaneously in a manner “floating freely” between an upper and a lower polishing plate covered with a polishing pad. This polishing method is effected with supply of a polishing agent slurry containing abrasives, normally in general on the basis of a silica sol.
A suitable double-side polishing machine is described in DE 100 07 390 A1, which is hereby incorporated by reference herein.
In the case of chemical mechanical polishing (CMP), which, by contrast, comprises a final polishing only of the front side (“component side”) using a softer polishing pad as so-called haze-free polishing (“finishing”), abrasives are likewise supplied in the form of a polishing agent slurry.
The semiconductor wafer to be polished is usually a silicon wafer or a substrate having layer structures derived from silicon (e.g. silicon-germanium). Said silicon wafers are used in particular for producing semiconductor components such as memory chips (DRAM), microprocessors, sensors, light emitting diodes and many more.
The requirements made of silicon wafers for fabricating, in particular, memory chips and microprocessors are becoming more stringent. This concerns firstly the crystal properties themselves (e.g. with regard to the defect densities, internal getters for trapping metallic impurities), but in particular also the geometry and the flatness of the wafer. A silicon wafer having two perfectly plane-parallel sides, excellent flatness in particular on that side of the silicon wafer on which components are to be fabricated, and low surface roughness would be desirable. It would furthermore be desirable to be able to utilize the entire area of the component side, which is currently not possible on account of a decrease in thickness at the edge of the wafer and poor geometry in the edge region.
It is known that the conventional methods for polishing semiconductor wafers are responsible for this edge roll-off.
The edge geometry is usually quantified by specifying one or more edge roll-off parameters which usually relate to the total thickness of a silicon wafer or to the edge geometry of its front and/or rear side and which can be used to characterize the customarily observed decrease in the thickness of the silicon wafer in its edge region or the flatness of front and/or rear side of the silicon wafer likewise in its edge region. A method for measuring the edge roll-off of silicon wafers is described in Jpn. J. Appl. Phys. Vol. 38 (1999), pp. 38-39.
The polishing of semiconductor wafers by means of “Fixed Abrasive Polishing” (FAP) is furthermore known, in which the semiconductor wafer is polished on a polishing pad containing an abrasive material bonded in the polishing pad (“fixed-abrasive pad”).
A polishing step in which such an FAP polishing pad is used is referred to hereinafter for short as an FAP step.
DSP and CMP differ from FAP in particular by virtue of the fact that in DSP and CMP the polishing pad comprises no abrasives and abrasives are always supplied in the form of a polishing agent slurry.
The German patent application DE 102 007 035 266 A1 describes a method for polishing a substrate composed of silicon material, comprising two polishing steps of the FAP type, which differ in that, in one polishing step, a polishing agent slurry containing non-bonded abrasive material as solid material is introduced between the substrate and the polishing pad, while in the second polishing step the polishing agent slurry is replaced by a polishing agent solution that is free of solid materials.